
DS1254
10 of 17
Figure 5. Memory Write Cycle Timing, Write-Enable Controlled (Notes 5, 6, 8, 10, 11, 12,
and 13)
Figure 6. Memory Write Cycle Timing, Chip-Enable Controlled (Notes 5, 7, 8, 10, 11, 12,
and 13)
tWC
tAH1
tAW
tOEW
tDS
DATA IN
STABLE
tDH1
tODW
tWP
ADDRESS
CE
WE
DQ0–DQ7
tWC
tAH2
tAW
tDS
tDH2
tCOE
tODW
tWP
ADDRESS
CE
WE
DQ0–DQ7
DATA IN
STABLE